Datasheet

• FIFO for storing change of flow information and event only data
• Source address of conditional branches taken
• Destination address of indirect JMP and JSR instruction
• Destination address of interrupts, RTI, RTC, and RTS instruction
• Data associated with Event B trigger modes
• Ability to End-trace until reset and begin-trace from reset
24.1.2 Modes of operation
The on-chip ICE system can be enabled in all MCU functional modes. The DBG module
is disabled if the MCU is secure. The DBG module comparators are disabled when
executing a Background Debug Mode (BDM) command.
24.1.3 Block diagram
The following figure shows the structure of the DBG module.
Introduction
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
612 Freescale Semiconductor, Inc.