Datasheet

mmu_ppage_access
1
Comparator A
Address/Data/Control Registers
Tag
Force
Address Bus[16:0]
match_A
control
Read Data Bus
Read/Write
store
m
u
x
FIFO Data
ppage_sel
1
MCU in BDM
Change of Flow Indicators
subtract 2
m
u
x
Read DBGFH
Read DBGFL
register
Instr. Lastcycle
Bus Clk
Comparator B
match_B
8 deep
FIFO
m
u
x
event only
Write Data Bus
Trigger
Break
Control
Logic
c
o
n
t
r
o
FIFO Data
DBG Read Data Bus
DBG Module Enable
addr[16:0]
1
m
u
x
Write Data Bus
Read Data Bus
Read/Write
l
Comparator C
match_C
MCU reset
core_cof[1:0]
Read DBGFX
Figure 24-1. DBG block diagram
24.2 Signal description
The DBG module contains no external signals.
24.3 Memory map and registers
This section provides a detailed description of all DBG registers accessible to the end
user.
Chapter 24 Debug module (DBG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 613