Datasheet

DBG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3010 Debug Comparator A High Register (DBG_CAH) 8 R/W FFh 24.3.1/614
3011 Debug Comparator A Low Register (DBG_CAL) 8 R/W FEh 24.3.2/615
3012 Debug Comparator B High Register (DBG_CBH) 8 R/W 00h 24.3.3/616
3013 Debug Comparator B Low Register (DBG_CBL) 8 R/W 00h 24.3.4/616
3014 Debug Comparator C High Register (DBG_CCH) 8 R/W 00h 24.3.5/617
3015 Debug Comparator C Low Register (DBG_CCL) 8 R/W 00h 24.3.6/618
3016 Debug FIFO High Register (DBG_FH) 8 R 00h 24.3.7/618
3017 Debug FIFO Low Register (DBG_FL) 8 R 00h 24.3.8/619
3018 Debug Comparator A Extension Register (DBG_CAX) 8 R/W 00h 24.3.9/620
3019 Debug Comparator B Extension Register (DBG_CBX) 8 R/W 00h
24.3.10/
621
301A Debug Comparator C Extension Register (DBG_CCX) 8 R/W 00h
24.3.11/
622
301B Debug FIFO Extended Information Register (DBG_FX) 8 R 00h
24.3.12/
623
301C Debug Control Register (DBG_C) 8 R/W C0h
24.3.13/
623
301D Debug Trigger Register (DBG_T) 8 R/W 40h
24.3.14/
624
301E Debug Status Register (DBG_S) 8 R 01h
24.3.15/
626
301F Debug Count Status Register (DBG_CNT) 8 R 00h
24.3.16/
627
24.3.1 Debug Comparator A High Register (DBG_CAH)
NOTE
All the bits in this register reset to 1 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 0h offset = 3010h
Bit 7 6 5 4 3 2 1 0
Read
CA[15:8]
Write
Reset
1 1 1 1 1 1 1 1
Memory map and registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
614 Freescale Semiconductor, Inc.