Datasheet

DBG_CAH field descriptions
Field Description
7–0
CA[15:8]
Comparator A High Compare Bits
The Comparator A High compare bits control whether Comparator A will compare the address bus bits
[15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
24.3.2 Debug Comparator A Low Register (DBG_CAL)
NOTE
All the bits in this register reset to 1 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 1h offset = 3011h
Bit 7 6 5 4 3 2 1 0
Read
CA[7:0]
Write
Reset
1 1 1 1 1 1 1 0
DBG_CAL field descriptions
Field Description
7–0
CA[7:0]
Comparator A Low
The Comparator A Low compare bits control whether Comparator A will compare the address bus bits
[7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
Chapter 24 Debug module (DBG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 615