Datasheet

24.3.3 Debug Comparator B High Register (DBG_CBH)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 2h offset = 3012h
Bit 7 6 5 4 3 2 1 0
Read
CB[15:8]
Write
Reset
0 0 0 0 0 0 0 0
DBG_CBH field descriptions
Field Description
7–0
CB[15:8]
Comparator B High Compare Bits
The Comparator B High compare bits control whether Comparator B will compare the address bus bits
[15:8] to a logic 1 or logic 0.Not used in full mode.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
24.3.4 Debug Comparator B Low Register (DBG_CBL)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 3h offset = 3013h
Bit 7 6 5 4 3 2 1 0
Read
CB[7:0]
Write
Reset
0 0 0 0 0 0 0 0
Memory map and registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
616 Freescale Semiconductor, Inc.