Datasheet

DBG_CBL field descriptions
Field Description
7–0
CB[7:0]
Comparator B Low
The Comparator B Low compare bits control whether Comparator B will compare the address bus bits
[7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
24.3.5 Debug Comparator C High Register (DBG_CCH)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 4h offset = 3014h
Bit 7 6 5 4 3 2 1 0
Read
CC[15:8]
Write
Reset
0 0 0 0 0 0 0 0
DBG_CCH field descriptions
Field Description
7–0
CC[15:8]
Comparator C High Compare Bits
The Comparator C High compare bits control whether Comparator C will compare the address bus bits
[15:8] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
Chapter 24 Debug module (DBG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 617