Datasheet

24.3.6 Debug Comparator C Low Register (DBG_CCL)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 5h offset = 3015h
Bit 7 6 5 4 3 2 1 0
Read
CC[7:0]
Write
Reset
0 0 0 0 0 0 0 0
DBG_CCL field descriptions
Field Description
7–0
CC[7:0]
Comparator C Low
The Comparator C Low compare bits control whether Comparator C will compare the address bus bits
[7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0.
1 Compare corresponding address bit to a logic 1.
24.3.7 Debug FIFO High Register (DBG_FH)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 6h offset = 3016h
Bit 7 6 5 4 3 2 1 0
Read F[15:8]
Write
Reset
0 0 0 0 0 0 0 0
Memory map and registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
618 Freescale Semiconductor, Inc.