Datasheet

24.3.9 Debug Comparator A Extension Register (DBG_CAX)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 8h offset = 3018h
Bit 7 6 5 4 3 2 1 0
Read
RWAEN RWA
0
Write
Reset
0 0 0 0 0 0 0 0
DBG_CAX field descriptions
Field Description
7
RWAEN
Read/Write Comparator A Enable Bit
The RWAEN bit controls whether read or write comparison is enabled for Comparator A.
0 Read/Write is not used in comparison.
1 Read/Write is used in comparison.
6
RWA
Read/Write Comparator A Value Bit
The RWA bit controls whether read or write is used in compare for Comparator A. The RWA bit is not used
if RWAEN = 0.
0 Write cycle will be matched.
1 Read cycle will be matched.
5–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Memory map and registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
620 Freescale Semiconductor, Inc.