Datasheet

24.3.10 Debug Comparator B Extension Register (DBG_CBX)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + 9h offset = 3019h
Bit 7 6 5 4 3 2 1 0
Read
RWBEN RWB
0
Write
Reset
0 0 0 0 0 0 0 0
DBG_CBX field descriptions
Field Description
7
RWBEN
Read/Write Comparator B Enable Bit
The RWBEN bit controls whether read or write comparison is enabled for Comparator B. In full modes,
RWAEN and RWA are used to control comparison of R/W and RWBEN is ignored.
0 Read/Write is not used in comparison.
1 Read/Write is used in comparison.
6
RWB
Read/Write Comparator B Value Bit
The RWB bit controls whether read or write is used in compare for Comparator B. The RWB bit is not used
if RWBEN = 0.In full modes, RWAEN and RWA are used to control comparison of R/W and RWB is
ignored.
0 Write cycle will be matched.
1 Read cycle will be matched.
5–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 24 Debug module (DBG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 621