Datasheet

24.3.12 Debug FIFO Extended Information Register (DBG_FX)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 3010h base + Bh offset = 301Bh
Bit 7 6 5 4 3 2 1 0
Read PPACC 0 Bit16
Write
Reset
0 0 0 0 0 0 0 0
DBG_FX field descriptions
Field Description
7
PPACC
PPAGE Access Indicator Bit
This bit indicates whether the captured information in the current FIFO word is associated with an
extended access through the PPAGE mechanism or not. This is indicated by the internal signal
mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism.
0 The information in the corresponding FIFO word is event-only data or an unpaged 17-bit CPU address
with bit-16 = 0.
1 The information in the corresponding FIFO word is a 17-bit flash address with PPAGE[2:0] in the three
most significant bits and CPU address[13:0] in the 14 least significant bits.
6–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Bit16
Extended Address Bit 16
This bit is the most significant bit of the 17-bit core address.
24.3.13 Debug Control Register (DBG_C)
Address: 3010h base + Ch offset = 301Ch
Bit 7 6 5 4 3 2 1 0
Read
DBGEN ARM TAG BRKEN
0
LOOP1
Write
Reset
1 1 0 0 0 0 0 0
Chapter 24 Debug module (DBG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 623