Datasheet

NOTE
The DBG trigger register (DBGT) can not be changed unless
ARM=0.
Address: 3010h base + Dh offset = 301Dh
Bit 7 6 5 4 3 2 1 0
Read
TRGSEL BEGIN
0
TRG
Write
Reset
0 1 0 0 0 0 0 0
DBG_T field descriptions
Field Description
7
TRGSEL
Trigger Selection Bit
The TRGSEL bit controls the triggering condition for the comparators.
0 Trigger on any compare address access.
1 Trigger if opcode at compare address is execute.
6
BEGIN
Begin/End Trigger Bit
The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO.
0 Trigger at end of stored data.
1 Trigger before storing data.
5–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
TRG
Trigger Mode Bits
The TRG bits select the trigger mode of the DBG module.
0000 A only.
0001 A or B.
0010 A then B.
0011 Event only B.
0100 A then event only B.
0101 A and B (full mode).
0110 A and not B (full mode).
0111 Inside range.
1000 Outside range.
1001-1111 No trigger.
Chapter 24 Debug module (DBG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 625