Datasheet

24.3.15 Debug Status Register (DBG_S)
NOTE
The figure shows the values in POR or non-end-run reset. The
bits of AF, BF and CF are undefined and ARMF is reset to 0 in
end-run reset. In the case of an end-trace to reset where
DBGEN=1 and BEGIN=0, ARMF gets cleared by reset but AF,
BF, and CF do not change after reset.
Address: 3010h base + Eh offset = 301Eh
Bit 7 6 5 4 3 2 1 0
Read AF BF CF 0 ARMF
Write
Reset
0 0 0 0 0 0 0 1
DBG_S field descriptions
Field Description
7
AF
Trigger A Match Bit
The AF bit indicates if Trigger A match condition was met since arming.
0 Comparator A did not match.
1 Comparator A match.
6
BF
Trigger B Match Bit
The BF bit indicates if Trigger B match condition was met since arming.
0 Comparator B did not match.
1 Comparator B match.
5
CF
Trigger C Match Bit
The CF bit indicates if Trigger C match condition was met since arming.
0 Comparator C did not match.
1 Comparator C match.
4–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
ARMF
Arm Flag Bit
The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill. While
DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC.
0 Debugger not armed.
1 Debugger armed.
Memory map and registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
626 Freescale Semiconductor, Inc.