Datasheet

Table 4-4. High-page register allocation (continued)
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x30C1
FTM2_CNTH
Bit 15 14 13 12 11 10 9 Bit 8
0x30C2 FTM2_CNTL Bit 7 6 5 4 3 2 1 Bit 0
0x30C3 FTM2_MODH Bit 15 14 13 12 11 10 9 Bit 8
0x30C4 FTM2_MODL Bit 7 6 5 4 3 2 1 Bit 0
0x30C5 FTM2_C0SC CHF CHIE MSB MSA ELSB ELSA — —
0x30C6 FTM2_C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x30C7 FTM2_C0VL Bit 7 6 5 4 3 2 1 Bit 0
0x30C8 FTM2_C1SC CHF CHIE MSB MSA ELSB ELSA — —
0x30C9 FTM2_C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x30CA FTM2_C1VL Bit 7 6 5 4 3 2 1 Bit 0
0x30CB FTM2_C2SC CHF CHIE MSB MSA ELSB ELSA — —
0x30CC FTM2_C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x30CD FTM2_C2VL Bit 7 6 5 4 3 2 1 Bit 0
0x30CE FTM2_C3SC CHF CHIE MSB MSA ELSB ELSA — —
0x30CF FTM2_C3VH Bit 15 14 13 12 11 10 9 Bit 8
0x30D0 FTM2_C3VL Bit 7 6 5 4 3 2 1 Bit 0
0x30D1 FTM2_C4SC CHF CHIE MSB MSA ELSB ELSA — —
0x30D2 FTM2_C4VH Bit 15 14 13 12 11 10 9 Bit 8
0x30D3 FTM2_C4VL Bit 7 6 5 4 3 2 1 Bit 0
0x30D4 FTM2_C5SC CHF CHIE MSB MSA ELSB ELSA — —
0x30D5 FTM2_C5VH Bit 15 14 13 12 11 10 9 Bit 8
0x30D6 FTM2_C5VL Bit 7 6 5 4 3 2 1 Bit 0
0x30D7 FTM2_CNTINH Bit 15 14 13 12 11 10 9 Bit 8
0x30D8 FTM2_CNTINL Bit 7 6 5 4 3 2 1 Bit 0
0x30D9 FTM2_STATUS CH7F CH6F CH5F CH4F CH3F CH2F CH1F CH0F
0x30DA FTM2_MODE
FAULTI
E
FAULTM
CAPTE
ST
PWMSY
NC
WPDIS INIT FTMEN
0x30DB FTM2_SYNC
SWSYN
C
TRIG2 TRIG1 TRIG0
SYNCH
OM
REINIT
CNTMA
X
CNTMIN
0x30DC FTM2_OUTINIT CH7OI CH6OI CH5OI CH4OI CH3OI CH2OI CH1OI CH0OI
0x30DD FTM2_OUTMASK CH7OM CH6OM CH5OM CH4OM CH3OM CH2OM CH1OM CH0OM
0x30DE FTM2_COMBINE0 —
FAULTE
N
SYNCE
N
DTEN DECAP
DECAP
EN
COMP
COMBI
NE
0x30DF FTM2_COMBINE1 —
FAULTE
N
SYNCE
N
DTEN DECAP
DECAP
EN
COMP
COMBI
NE
0x30E0 FTM2_COMBINE2 —
FAULTE
N
SYNCE
N
DTEN DECAP
DECAP
EN
COMP
COMBI
NE
0x30E1 FTM2_COMBINE3 —
FAULTE
N
SYNCE
N
DTEN DECAP
DECAP
EN
COMP
COMBI
NE
0x30E2 FTM2_DEATIME DTPS DTVAL
Table continues on the next page...
Register addresses and bit assignments
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
70 Freescale Semiconductor, Inc.