Datasheet

memory while commands are being executed on EEPROM

memory. It is not possible to read from EEPROM memory

while a command (erase/program) is executing on flash

memory. Simultaneous EEPROM memory are implemented

with error correction codes (ECC) that can resolve single bit

faults and detect double bit faults.

The following figure shows the block diagram of the flash and EEPROM module.

Divider

Clock

Command Interrupt Request

Protection

Registers

Security

Sector 1

Sector 127

Sector 0

FLASH

EEPROM

Interface

NVM controller

Bus Clock

Error Interrupt Request

CPU

16K

256

Sector 127

Flash

Figure 4-2. Flash and EEPROM block diagram

Flash features:

• 64 KB of flash memory composed of one 64 KB flash block divided into 128 sectors

of 512 bytes

• Automated program and erase algorithm with verification

• Fast sector erase and longword program operation

• Ability to read the flash memory while programming a word in the EEPROM

memory

• Flexible protection scheme to prevent accidental program or erase of flash memory

EEPROM features:

• 256 bytes of EEPROM memory composed of one 256 byte EEPROM block divided

into sectors of 2 bytes

• Single bit fault correction and double bit fault detection within a word during read

operations

• Automated program and erase algorithm with verification and generation of ECC

parity bits

• Fast sector erase and byte program operation

Flash and EEPROM

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

74 Freescale Semiconductor, Inc.