Datasheet

4.5.2.4.1 Writing the FCLKDIV register
Prior to issuing any flash and EEPROM program or erase command after a reset, the user
is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of
1MHz. The following table shows recommended values for the FDIV field based on
BUSCLK frequency.
Table 4-7. FDIV values for various BUSCLK frequencies
BUSCLK frequency
(MHz)
FDIV[5:0]
MIN
1
MAX
2
1.0 1.6 0x00
1.6 2.6 0x01
2.6 3.6 0x02
3.6 4.6 0x03
4.6 5.6 0x04
5.6 6.6 0x05
6.6 7.6 0x06
7.6 8.6 0x07
8.6 9.6 0x08
9.6 10.6 0x09
10.6 11.6 0x0A
11.6 12.6 0x0B
12.6 13.6 0x0C
13.6 14.6 0x0D
14.6 15.6 0x0E
15.6 16.6 0x0F
16.6 17.6 0x10
17.6 18.6 0x11
18.6 19.6 0x12
19.6 20.0 0x13
1. BUSCLK is greater than this value
2. BUSCLK is less than or equal to this value
CAUTION
Programming or erasing the flash and EEPROM memory
cannot be performed if the bus clock runs at less than 0.8 MHz.
Setting FCLKDIV[FDIV] too high can destroy the flash and
EEPROM memory due to overstress. Setting FCLKDIV[FDIV]
too low can result in incomplete programming or erasure of the
flash and EEPROM memory cells.
Chapter 4 Memory map
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 79