Datasheet

Section number Title Page
7.7.2 Port B Data Register (PORT_PTBD)..............................................................................................................157
7.7.3 Port C Data Register (PORT_PTCD)..............................................................................................................157
7.7.4 Port D Data Register (PORT_PTDD)..............................................................................................................158
7.7.5 Port E Data Register (PORT_PTED)...............................................................................................................158
7.7.6 Port F Data Register (PORT_PTFD)...............................................................................................................159
7.7.7 Port G Data Register (PORT_PTGD)..............................................................................................................159
7.7.8 Port H Data Register (PORT_PTHD)..............................................................................................................160
7.7.9 Port High Drive Enable Register (PORT_HDRVE)........................................................................................161
7.7.10 Port A Output Enable Register (PORT_PTAOE)............................................................................................162
7.7.11 Port B Output Enable Register (PORT_PTBOE)............................................................................................163
7.7.12 Port C Output Enable Register (PORT_PTCOE)............................................................................................164
7.7.13 Port D Output Enable Register (PORT_PTDOE)............................................................................................166
7.7.14 Port E Output Enable Register (PORT_PTEOE).............................................................................................167
7.7.15 Port F Output Enable Register (PORT_PTFOE).............................................................................................168
7.7.16 Port G Output Enable Register (PORT_PTGOE)............................................................................................169
7.7.17 Port H Output Enable Register (PORT_PTHOE)............................................................................................170
7.7.18 Port A Input Enable Register (PORT_PTAIE)................................................................................................171
7.7.19 Port B Input Enable Register (PORT_PTBIE)................................................................................................172
7.7.20 Port C Input Enable Register (PORT_PTCIE)................................................................................................173
7.7.21 Port D Input Enable Register (PORT_PTDIE)................................................................................................175
7.7.22 Port E Input Enable Register (PORT_PTEIE).................................................................................................176
7.7.23 Port F Input Enable Register (PORT_PTFIE).................................................................................................177
7.7.24 Port G Input Enable Register (PORT_PTGIE)................................................................................................178
7.7.25 Port H Input Enable Register (PORT_PTHIE)................................................................................................179
7.7.26 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................180
7.7.27 Port Filter Register 1 (PORT_IOFLT1)...........................................................................................................181
7.7.28 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................182
7.7.29 Port Clock Division Register (PORT_FCLKDIV)..........................................................................................183
7.7.30 Port A Pullup Enable Register (PORT_PTAPE).............................................................................................184
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
8 Freescale Semiconductor, Inc.