Datasheet

Table 4-9. Flash and EEPROM commands by mode and security state (continued)

FCMD Command

Unsecured Secured

0x0D Set user margin level * N/A

0x10 Erase verify EEPROM section * *

0x11 Program EEPROM * N/A

0x12 Erase EEPROM sector * N/A

1. Unsecured User mode

2. Secured User mode

4.5.2.5 Flash and EEPROM interrupts

The flash and EEPROM module can generate an interrupt when a flash command

operation has completed or when a flash and EEPROM command operation has detected

an ECC fault.

Table 4-10. Flash interrupt source

Interrupt source Interrupt flag Local enable Global (CCR) mask

Flash and EEPROM command complete

CCIF

(FSTAT register)

CCIE

(FCNFG register)

I Bit

ECC double bit fault on flash and EEPROM read

DFDIF

(FERSTAT register)

DFDIE

(FERCNFG register)

I Bit

ECC single bit fault on flash and EEPROM read

SFDIF

(FERSTAT register)

SFDIE

(FERCNFG register)

I Bit

4.5.2.5.1 Description of flash and EEPROM interrupt operation

The flash module uses the FSTAT[CCIF] flag in combination with the FCNFG[CCIE]

interrupt enable bit to generate the flash command interrupt request. The flash module

uses the DFDIF and SFDIF flags in combination with the FERSTAT[DFDIE] and

FERSTAT[SFDIE] interrupt enable bits to generate the flash error interrupt request.

The logic used for generating the flash module interrupts is shown in the following

figure.

Flash and EEPROM

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

82 Freescale Semiconductor, Inc.