Datasheet

Scenario 4
Scenario 6
Scenario 7
Scenario 5
FPHDIS = 1
FPLDIS = 1
FPHDIS = 1
FPLDIS = 0
FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
Protected region
not defined by FPLS, FPHS
Unprotected region
Protected region with size
defined by FPLS
Protected region with size
defined by FPHS
FPLS[1:0]
FPHS[1:0]
FPHS[1:0]
FPLS[1:0]
FPOPEN = 1
FPOPEN = 1
FPOPEN = 1FPOPEN = 1
Scenario 3
Scenario 2
Scenario 1
Scenario 0
Flash Start Address
0x8000
0xFFFF
Flash Start Address
0x8000
0xFFFF
FPOPEN = 0FPOPEN = 0FPOPEN = 0FPOPEN = 0FPOPEN = 0
Figure 4-6. Flash protection scenarios
The general guideline is that flash protection can only be added and not removed. The
following table specifies all valid transitions between flash protection scenarios. Any
attempt to write an invalid scenario to the FPROT register will be ignored. The contents
of the FPROT register reflect the active protection scenario. See the FPROT[FPHS] and
FPROT[FPLS] bit descriptions for additional restrictions.
Chapter 4 Memory map
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 85