Datasheet

Table 4-13. Flash protection scenario transitions
From protection
scenario
To protection scenario
0 1 2 3 4 5 6 7
0 × × × ×
1 × ×
2 × ×
3 ×
4 × ×
5 × × × ×
6 × × × ×
7 × × × × × × × ×
The flash protection address range is listed in the following two tables regarding the
scenarios in the table above.
Table 4-14. Flash protection higher address range
FPHS[1:0] Global address range Protected size
00 0xF800 – 0xFFFF 2 Kbytes
01 0xF000 – 0xFFFF 4 Kbytes
10 0xE000 – 0xFFFF 8 Kbytes
11 0xC000 – 0xFFFF 16 Kbytes
Table 4-15. Flash protection lower address range
FPLS[1:0] Global address range Protected size
00 0x8000 – 0x83FF 1 Kbytes
01 0x8000 – 0x87FF 2 Kbytes
10 0x8000 – 0x8FFF 4 Kbytes
11 0x8000 – 0x9FFF 8 Kbytes
During the reset sequence, fields NVM_EEPROT[DPOPEN] and NVM_EEPROT[DPS]
are loaded with the contents of the EEPROM protection byte in the flash configuration
field at global address 0xFF7D located in flash memory. EEPROM protection address
range is specified by the NVM_EEPROT[DPS].
Table 4-16. EEPROM protection address range
DPS[2:0] Global address range Protected size
000 0x3100 – 0x311F 32 bytes
001 0x3100 – 0x313F 64 bytes
010 0x3100 – 0x315F 96 bytes
Table continues on the next page...
Flash and EEPROM
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
86 Freescale Semiconductor, Inc.