Datasheet
Section number Title Page
7.7.31 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................185
7.7.32 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................186
7.7.33 Port D Pullup Enable Register (PORT_PTDPE).............................................................................................188
7.7.34 Port E Pullup Enable Register (PORT_PTEPE)..............................................................................................189
7.7.35 Port F Pullup Enable Register (PORT_PTFPE)..............................................................................................190
7.7.36 Port G Pullup Enable Register (PORT_PTGPE).............................................................................................192
7.7.37 Port H Pullup Enable Register (PORT_PTHPE).............................................................................................193
Chapter 8
Clock management
8.1 Clock module..................................................................................................................................................................195
8.2 Internal clock source (ICS).............................................................................................................................................197
8.2.1 Function description.........................................................................................................................................197
8.2.1.1 Bus frequency divider....................................................................................................................198
8.2.1.2 Low power bit usage......................................................................................................................198
8.2.1.3 Internal reference clock (ICSIRCLK)............................................................................................198
8.2.1.4 Fixed frequency clock (ICSFFCLK)..............................................................................................199
8.2.1.5 BDC clock......................................................................................................................................200
8.2.2 Modes of operation..........................................................................................................................................200
8.2.2.1 FLL engaged internal (FEI)...........................................................................................................201
8.2.2.2 FLL engaged external (FEE)..........................................................................................................201
8.2.2.3 FLL bypassed internal (FBI)..........................................................................................................201
8.2.2.4 FLL bypassed internal low power (FBILP)...................................................................................202
8.2.2.5 FLL bypassed external (FBE)........................................................................................................202
8.2.2.6 FLL bypassed external low power (FBELP).................................................................................203
8.2.2.7 Stop (STOP)...................................................................................................................................203
8.2.3 FLL lock and clock monitor.............................................................................................................................204
8.2.3.1 FLL clock lock...............................................................................................................................204
8.2.3.2 External reference clock monitor...................................................................................................204
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 9