Datasheet
4.5.2.8.3 Allowed simultaneous flash and EEPROM operations
Only the operations marked 'OK' in the following table are permitted to be run
simultaneously on the flash and EEPROM blocks. Some operations cannot be executed
simultaneously because certain hardware resources are shared by the two memories. The
priority has been placed on permitting flash reads while program and erase operations
execute on the EEPROM, providing read (flash) while write (EEPROM) functionality.
Table 4-19. Allowed simultaneous flash and EEPROM operations
Program flash
EEPROM
Read Margin read Program Sector erase Mass erase
Read OK OK OK
Margin Read
1
Program
Sector Erase
Mass Erase
2
OK
1. A 'Margin read' is any read after executing the margin setting commands 'Set user margin level' or 'Set field margin level'
with anything but the 'normal' level specified. See the Note on margin settings in
2. The 'Mass erase' operations are commands 'Erase all blocks' and 'Erase flash block'
4.5.2.9 Flash and EEPROM command summary
This section provides details of all available flash commands launched by a command
write sequence. The FSTAT[ACCERR] bit will be set during the command write
sequence if any of the following illegal steps are performed, causing the command not to
be processed by the memory controller:
• Starting any command write sequence that programs or erases flash memory before
initializing the FLCKDIV register.
• Writing an invalid command as part of the command write sequence.
• For additional possible errors, refer to the error handling table provided for each
command.
If a flash block is read during the execution of an algorithm (FSTAT[CCIF] = 0) on that
same block, the read operation will return invalid data if both flags FERSTAT[SFDIF]
and FERSTAT[DFDIF] are set. If the FERSTAT[SFDIF] or FERSTAT[DFDIF] flags
were not previously set when the invalid read operation occurred, both the
FERSTAT[SFDIF] and FERSTAT[DFDIF] flags will be set.
If the FSTAT[ACCERR] or FSTAT[FPVIOL] bits are set, the user must clear these bits
before starting any command write sequence.
Chapter 4 Memory map
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 91