Datasheet

MC9S08QB8 Series MCU Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor18
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1 Control Timing
Figure 13. Reset Timing
Table 12. Control Timing
Num C Rating Symbol Min Typical
1
1
Typical values are based on characterization data at V
DD
= 3.0 V, 25 °C unless otherwise stated.
Max Unit
1D
Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
DC 10 MHz
2 D Internal low power oscillator period
t
LPO
700 1300 μs
3D
External reset pulse width
2
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
t
extrst
100 ns
4 D Reset low drive
t
rstdrv
34 x t
cyc
——ns
5D
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
t
MSSU
500 ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes
3
3
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH
after V
DD
rises above V
LVD
.
t
MSH
100 μs
7D
IRQ pulse width
Asynchronous path
2
Synchronous path
4
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
t
ILIH,
t
IHIL
100
1.5 x t
cyc
ns
8 D Keyboard interrupt pulse width
Asynchronous path
2
Synchronous path
4
t
ILIH,
t
IHIL
100
1.5 x t
cyc
ns
9D
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40°C to 85°C.
t
Rise
, t
Fall
16
23
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise
, t
Fall
5
9
ns
10 D
Voltage regulator recovery time t
VRR
—4μs
t
extrst
RESET PIN