Datasheet

Electrical Characteristics
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor 23
Figure 15. Deviation of DCO Output Across Temperature at V
DD
= 3.0 V
8C
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δf
dco_t
—
+ 0.5
-1.0
± 2
%f
dco
9C
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0
°C to 70 °C
Δf
dco_t
— ± 0.5 ± 1
%f
dco
10 C
FLL acquisition time
3
t
Acquire
—— 1ms
11 C
Long term jitter of DCO output clock (averaged over 2-ms
interval)
4
C
Jitter
— 0.02 0.2
%f
dco
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage for a
given interval.
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num C Characteristic Symbol Min Typ
1
Max Unit
-1.00%
-0.80%
-0.60%
-0.40%
-0.20%
0.00%
0.20%
0.40%
0.60%
-40 -20 0 20 40 60 80 100 120
VDD
% deviation