Datasheet

Electrical Characteristics
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor 25
Figure 17. Reset Timing
Figure 18. IRQ
/KBIPx Timing
7D
IRQ pulse width
Asynchronous path
2
Synchronous path
4
t
ILIH,
t
IHIL
100
1.5 x t
cyc
—
—
—
—
ns
8D
Keyboard interrupt pulse width
Asynchronous path
2
Synchronous path
4
t
ILIH,
t
IHIL
100
1.5 x t
cyc
—
—
—
—
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise
, t
Fall
—
—
8
31
—
—
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise
, t
Fall
—
—
7
24
—
—
ns
10
Voltage regulator recovery time t
VRR
—4—μs
1
Typical values are based on characterization data at V
DD
= 3.0V, 25°C unless otherwise stated.
2
This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH
after V
DD
rises above V
LVD
.
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40°C to 85°C.
Table 13. Control Timing (continued)
Num C Rating Symbol Min Typ
1
Max Unit
t
extrst
RESET PIN
t
IHIL
KBIPx
t
ILIH
IRQ/KBIPx