Datasheet

Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
118 Freescale Semiconductor
9.1.1.3 Alternate Clock
The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
or the local asynchronous clock (ADACK) within the module. The alternate clock, ALTCLK, input for the
MC9S08QG8/4 MCU devices is not implemented.
9.1.1.4 Hardware Trigger
The ADC hardware trigger, ADHWT, is output from the real-time interrupt (RTI) counter. The RTI counter
can be clocked by either ICSERCLK or a nominal 1-kHz clock source within the RTI block.
The period of the RTI is determined by the input clock frequency and the RTIS bits. The RTI counter is a
free running counter that generates an overflow at the RTI rate determined by the RTIS bits. When the
ADC hardware trigger is enabled, a conversion is initiated upon an RTI counter overflow.
The RTI can be configured to cause a hardware trigger in MCU run, wait, and stop3.
9.1.1.5 Analog Pin Enables
The ADC on MC9S08QG8 devices contains only one analog pin enable register, APCTL1.
9.1.1.6 Temperature Sensor
The ADC module includes a temperature sensor whose output is connected to one of the ADC analog
channel inputs. Equation 9-1 provides an approximate transfer function of the temperature sensor.
Temp = 25 - ((V
TEMP
-V
TEMP25
) ÷ m) Eqn. 9-1
where:
—V
TEMP
is the voltage of the temperature sensor channel at the ambient temperature.
—V
TEMP25
is the voltage of the temperature sensor channel at 25°C.
— m is the hot or cold voltage versus temperature slope in V/°C.
For temperature calculations, use the V
TEMP25
and m values from Section A.10, “ADC Characteristics,”
in Appendix A, “Electrical Characteristics.”
In application code, the user reads the temperature sensor channel, calculates V
TEMP
, and compares to
V
TEMP25
. If V
TEMP
is greater than V
TEMP25
, the cold slope value is applied in Equation 9-1. If V
TEMP
is
less than V
TEMP25
the hot slope value is applied in Equation 9-1.
9.1.1.7 Low-Power Mode Operation
The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set.