Datasheet

MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor 33
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08QG8/4 are described in this section. Entry into each mode, exit from
each mode, and functionality while in each mode are described.
3.2 Features
• Active background mode for code development
• Wait mode:
— CPU halts operation to conserve power
— System clocks running
— Full voltage regulation is maintained
• Stop modes: CPU and bus clocks stopped
— Stop1: Full powerdown of internal circuits for maximum power savings
— Stop2: Partial powerdown of internal circuits; RAM contents retained
— Stop3: All internal circuits powered for fast recovery; RAM and register contents are retained
3.3 Run Mode
Run is the normal operating mode for the MC9S08QG8/4. This mode is selected upon the MCU exiting
reset if the BKGD/MS pin is high. In this mode, the CPU executes code from internal memory with
execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provides the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low during POR or immediately after issuing a background debug
force reset (see 5.8.3, “System Background Debug Force Reset Register (SBDFR)”)
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint