Datasheet

Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor 71
5.8.5 System Options Register 2 (SOPT2)
This high page register contains bits to configure MCU specific features on the MC9S08QG8/4 devices.
76543210
R
COPCLKS
1
1
This bit can be written only one time after reset. Additional writes are ignored.
00000
IICPS ACIC
W
Reset:00000000
= Unimplemented or Reserved
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Field Description
7
COPCLKS
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
1
IICPS
IIC Pin Select— This bit selects the location of the SDA and SCL pins of the IIC module.
0 SDA on PTA2, SCL on PTA3.
1 SDA on PTB6, SCL on PTB7.
0
ACIC
Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM input channel 0.
0 ACMP output not connected to TPM input channel 0.
1 ACMP output connected to TPM input channel 0.