Datasheet

Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
184 Freescale Semiconductor
13.1.4 Block Diagram
The block diagram for the modulo timer module is shown Figure 13-2.
Figure 13-2. Modulo Timer (MTIM) Block Diagram
13.2 External Signal Description
The MTIM includes one external signal, TCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TCLK are shown in Table 13-1.
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter
must be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for
the pin location and priority of this function.
13.3 Register Definition
Figure 13-3 is a summary of MTIM registers.
Table 13-1. Signal Properties
Signal Function I/O
TCLK External clock source input into MTIM I
BUSCLK
TCLK
SYNC
CLOCK
SOURCE
SELECT
PRESCALE
AND SELECT
DIVIDE BY
8-BIT COUNTER
(MTIMCNT)
8-BIT MODULO
(MTIMMOD)
8-BIT COMPARATOR
TRST
TSTP
CLKS
PS
XCLK
TOIE
MTIM
INTERRU
PT
TOF