Datasheet

Chapter 1 Device Overview
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor 21
Table 1-2 provides the functional versions of the on-chip modules.
System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function. All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
Table 1-2. Versions of On-Chip Modules
Module Version
Analog Comparator (ACMP) 2
Analog-to-Digital Converter (ADC) 1
Central Processing Unit (CPU) 2
IIC Module (IIC) 1
Internal Clock Source (ICS) 1
Keyboard Interrupt (KBI) 2
Modulo Timer (MTIM) 1
Serial Communications Interface (SCI) 3
Serial Peripheral Interface (SPI) 3
Timer Pulse-Width Modulator (TPM) 2
Low-Power Oscillator (XOSC) 1
Debug Module (DBG) 2
TPM MTIM IIC SCI SPI
CPU
BDC
ADC
FLASH
ICS
ICSOUT
÷2
ICSFFE
SYSTEM
LOGIC
BUSCLK
ICSLCLK**
CONTROL
FIXED FREQ CLOCK (XCLK)
ICSERCLK*
RTI
* ICSERCLK requires XOSC module.
** ICSLCLK is the alternate BDC clock source for the MC9S08QG8/4.
÷2
FLASH has frequency
requirements for
program
and erase operation.
See Appendix A,
“Electrical
Characteristics.”
ADC has min and max
frequency requirements.
See the ADC chapter
and
Appendix A, “Electrical
Characteristics.”
ICSFFCLK
XOSC
EXTAL
XTAL
COP1-kHz
TCLK