Datasheet

Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor 75
5.8.9 System Power Management Status and Control 2 Register
(SPMSC2)
This high page register contains status and control bits to configure the stop mode behavior of the MCU.
See Section 3.6, “Stop Modes,” for more information on stop modes.
76543210
R 0 0 0 PDF PPDF 0
PDC
1
1
This bit can be written only one time after reset. Additional writes are ignored.
PPDC
1
W PPDACK
Reset:00000000
= Unimplemented or Reserved
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
Table 5-13. SPMSC2 Register Field Descriptions
Field Description
4
PDF
Power Down Flag — This read-only status bit indicates the MCU has recovered from stop1 mode.
0 MCU has not recovered from stop1 mode.
1 MCU recovered from stop1 mode.
3
PPDF
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF and the PDF bits.
1
PDC
Power Down Control — The PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
0
PPDC
Partial Power Down Control — The PPDC bit controls which power down mode is selected.
0 Stop1 full power down mode enabled if PDC set.
1 Stop2 partial power down mode enabled if PDC set.