Datasheet

MC9S08SF4 Series MCU Data Sheet, Rev. 4
AC Characteristics
Freescale Semiconductor18
3.9.1 Control Timing
Figure 14. Reset Timing
Figure 15. IRQ/KBIPx Timing
Table 9. Control Timing
Parameter Symbol Minimum Typical
1
1
Data in Typical column was characterized at 5.0 V, 25 C.
Maximum Unit
Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
1—20MHz
External reset pulse width
2
2
This is the shortest pulse that is guaranteed to be recognized.
t
extrst
100 — — ns
IRQ pulse width
Asynchronous path
2
Synchronous path
3
3
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
t
ILIH,
t
IHIL
100
1.5 t
cyc
——ns
KBIPx pulse width
Asynchronous path
2
Synchronous path
3
t
ILIH,
t
IHIL
100
1.5 t
cyc
——ns
Port rise and fall time (load = 50 pF)
4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
4
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40 C to 125 C.
t
Rise
, t
Fall
—
—
3
30
—
—
ns
BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
t
MSSU
500 — — ns
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes
5
5
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH
after V
DD
rises above V
LVD
.
t
MSH
100 — — s
t
extrst
RESET PIN
t
IHIL
IRQ/KBIPx
t
ILIH
IRQ/KBIPx