Datasheet

Chapter 16 Timer/PWM Module (S08TPMV3)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
264 Freescale Semiconductor
In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty
cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current
PWM period (when the count reaches 0x0000).
— TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4]
In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting.
Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting.
6. Write to TPMxMODH:L registers in BDM mode (Section 16.3.3, “TPM Counter Modulo
Registers (TPMxMODH:TPMxMODL))
In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism
of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when
there is a write to TPMxSC register.
7. Update of EPWM signal when CLKSB:CLKSA = 00
In the TPM v3 if CLKSB:CLKSA = 00, then the EPWM signal in the channel output is not update
(it is frozen while CLKSB:CLKSA = 00). Instead, in the TPM v2 the EPWM signal is updated at
the next rising edge of bus clock after a write to TPMxCnSC register.
The Figure 0-1 and Figure 0-2 show when the EPWM signals generated by TPM v2 and TPM v3
after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register.
Figure 0-1. Generation of high-true EPWM signal by TPM v2 and v3 after the reset
ELSnB:ELSnA BITS
CLKSB:CLKSA BITS
0
TPMxMODH:TPMxMODL = 0x0007
TPMxCnVH:TPMxCnVL = 0x0005
TPMxCNTH:TPMxCNTL
TPMv2 TPMxCHn
EPWM mode
00
00 10
BUS CLOCK
01
1234567012
CHnF BIT
MSnB:MSnA BITS
00 10
(in TPMv2 and TPMv3)
TPMv3 TPMxCHn
...
RESET (active low)