Datasheet
Table Of Contents
- MC9S08SH8DS_Readme
- MC9S08SH8_DSAD_Rev.1
- MC9S08SH8
- Chapter 1 Device Overview
- Chapter 2 Pins and Connections
- Chapter 3 Modes of Operation
- Chapter 4 Memory
- Chapter 5 Resets, Interrupts, and General System Control
- 5.1 Introduction
- 5.2 Features
- 5.3 MCU Reset
- 5.4 Computer Operating Properly (COP) Watchdog
- 5.5 Interrupts
- 5.6 Low-Voltage Detect (LVD) System
- 5.7 Reset, Interrupt, and System Control Registers and Control Bits
- 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)
- 5.7.2 System Reset Status Register (SRS)
- 5.7.3 System Background Debug Force Reset Register (SBDFR)
- 5.7.4 System Options Register 1 (SOPT1)
- 5.7.5 System Options Register 2 (SOPT2)
- 5.7.6 System Device Identification Register (SDIDH, SDIDL)
- 5.7.7 System Power Management Status and Control 1 Register (SPMSC1)
- 5.7.8 System Power Management Status and Control 2 Register (SPMSC2)
- Chapter 6 Parallel Input/Output Control
- 6.1 Port Data and Data Direction
- 6.2 Pull-up, Slew Rate, and Drive Strength
- 6.3 Ganged Output
- 6.4 Pin Interrupts
- 6.5 Pin Behavior in Stop Modes
- 6.6 Parallel I/O and Pin Control Registers
- 6.6.1 Port A Registers
- 6.6.1.1 Port A Data Register (PTAD)
- 6.6.1.2 Port A Data Direction Register (PTADD)
- 6.6.1.3 Port A Pull Enable Register (PTAPE)
- 6.6.1.4 Port A Slew Rate Enable Register (PTASE)
- 6.6.1.5 Port A Drive Strength Selection Register (PTADS)
- 6.6.1.6 Port A Interrupt Status and Control Register (PTASC)
- 6.6.1.7 Port A Interrupt Pin Select Register (PTAPS)
- 6.6.1.8 Port A Interrupt Edge Select Register (PTAES)
- 6.6.2 Port B Registers
- 6.6.2.1 Port B Data Register (PTBD)
- 6.6.2.2 Port B Data Direction Register (PTBDD)
- 6.6.2.3 Port B Pull Enable Register (PTBPE)
- 6.6.2.4 Port B Slew Rate Enable Register (PTBSE)
- 6.6.2.5 Port B Drive Strength Selection Register (PTBDS)
- 6.6.2.6 Port B Interrupt Status and Control Register (PTBSC)
- 6.6.2.7 Port B Interrupt Pin Select Register (PTBPS)
- 6.6.2.8 Port B Interrupt Edge Select Register (PTBES)
- 6.6.3 Port C Registers
- 6.6.1 Port A Registers
- Chapter 7 Central Processor Unit (S08CPUV2)
- 7.1 Introduction
- 7.2 Programmer’s Model and CPU Registers
- 7.3 Addressing Modes
- 7.4 Special Operations
- 7.5 HCS08 Instruction Set Summary
- Chapter 8 Analog Comparator 5-V (S08ACMPV2)
- Chapter 9 Analog-to-Digital Converter (S08ADCV1)
- 9.1 Introduction
- 9.2 External Signal Description
- 9.3 Register Definition
- 9.3.1 Status and Control Register 1 (ADCSC1)
- 9.3.2 Status and Control Register 2 (ADCSC2)
- 9.3.3 Data Result High Register (ADCRH)
- 9.3.4 Data Result Low Register (ADCRL)
- 9.3.5 Compare Value High Register (ADCCVH)
- 9.3.6 Compare Value Low Register (ADCCVL)
- 9.3.7 Configuration Register (ADCCFG)
- 9.3.8 Pin Control 1 Register (APCTL1)
- 9.3.9 Pin Control 2 Register (APCTL2)
- 9.3.10 Pin Control 3 Register (APCTL3)
- 9.4 Functional Description
- 9.5 Initialization Information
- 9.6 Application Information
- Chapter 10 Internal Clock Source (S08ICSV2)
- 10.1 Introduction
- 10.2 External Signal Description
- 10.3 Register Definition
- 10.4 Functional Description
- Chapter 11 Inter-Integrated Circuit (S08IICV2)
- Chapter 12 Modulo Timer (S08MTIMV1)
- Chapter 13 Real-Time Counter (S08RTCV1)
- Chapter 14 Serial Communications Interface (S08SCIV4)
- Chapter 15 Serial Peripheral Interface (S08SPIV3)
- Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
- Chapter 17 Development Support
- 17.1 Introduction
- 17.2 Background Debug Controller (BDC)
- 17.3 On-Chip Debug System (DBG)
- 17.4 Register Definition
- 17.4.1 BDC Registers and Control Bits
- 17.4.2 System Background Debug Force Reset Register (SBDFR)
- 17.4.3 DBG Registers and Control Bits
- 17.4.3.1 Debug Comparator A High Register (DBGCAH)
- 17.4.3.2 Debug Comparator A Low Register (DBGCAL)
- 17.4.3.3 Debug Comparator B High Register (DBGCBH)
- 17.4.3.4 Debug Comparator B Low Register (DBGCBL)
- 17.4.3.5 Debug FIFO High Register (DBGFH)
- 17.4.3.6 Debug FIFO Low Register (DBGFL)
- 17.4.3.7 Debug Control Register (DBGC)
- 17.4.3.8 Debug Trigger Register (DBGT)
- 17.4.3.9 Debug Status Register (DBGS)
- Appendix A Electrical Characteristics
- A.1 Introduction
- A.2 Parameter Classification
- A.3 Absolute Maximum Ratings
- A.4 Thermal Characteristics
- A.5 ESD Protection and Latch-Up Immunity
- A.6 DC Characteristics
- A.7 Supply Current Characteristics
- A.8 External Oscillator (XOSC) Characteristics
- A.9 Internal Clock Source (ICS) Characteristics
- A.10 Analog Comparator (ACMP) Electricals
- A.11 ADC Characteristics
- A.12 AC Characteristics
- A.13 FLASH Specifications
- A.14 EMC Performance
- Appendix B Ordering Information and Mechanical Drawings
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
138 Freescale Semiconductor
9.4.4.2 Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high
at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if
the previous data is in the process of being read while in 10-bit MODE (the ADCRH register has been read
but the ADCRL register has not). When blocking is active, the data transfer is blocked, COCO is not set,
and the new result is lost. In the case of single conversions with the compare function enabled and the
compare condition false, blocking has no effect and ADC operation is terminated. In all other cases of
operation, when a data transfer is blocked, another conversion is initiated regardless of the state of ADCO
(single or continuous conversions enabled).
If single conversions are enabled, the blocking mechanism could result in several discarded conversions
and excess power consumption. To avoid this issue, the data registers must not be read after initiating a
single conversion until the conversion completes.
9.4.4.3 Aborting Conversions
Any conversion in progress will be aborted when:
• A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
• A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of
operation change has occurred and the current conversion is therefore invalid.
• The MCU is reset.
• The MCU enters stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case that
the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
9.4.4.4 Power Control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value
for f
ADCK
(see the electrical specifications).
9.4.4.5 Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit or 10-bit), and the frequency of the conversion clock (
f
ADCK
). After
the module becomes active, sampling of the input begins. ADLSMP is used to select between short and
long sample times.When sampling is complete, the converter is isolated from the input channel and a
successive approximation algorithm is performed to determine the digital value of the analog signal. The