Datasheet

Chapter 10 Internal Clock Source (S08ICSV2)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
154 Freescale Semiconductor
10.3.1 ICS Control Register 1 (ICSC1)
7 654 3 210
R
CLKS RDIV IREFS IRCLKEN IREFSTEN
W
Reset: 0 0 0 0 0 1 0 0
Figure 10-3. ICS Control Register 1 (ICSC1)
Table 10-2. ICS Control Register 1 Field Descriptions
Field Description
7:6
CLKS
Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
00 Output of FLL is selected.
01 Internal reference clock is selected.
10 External reference clock is selected.
11 Reserved, defaults to 00.
5:3
RDIV
Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits.
Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.
000 Encoding 0 — Divides reference clock by 1 (reset default)
001 Encoding 1 — Divides reference clock by 2
010 Encoding 2 — Divides reference clock by 4
011 Encoding 3 — Divides reference clock by 8
100 Encoding 4 — Divides reference clock by 16
101 Encoding 5 — Divides reference clock by 32
110 Encoding 6 — Divides reference clock by 64
111 Encoding 7 — Divides reference clock by 128
2
IREFS
Internal Reference Select — The IREFS bit selects the reference clock source for the FLL.
1 Internal reference clock selected
0 External reference clock selected
1
IRCLKEN
Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as
ICSIRCLK.
1 ICSIRCLK active
0 ICSIRCLK inactive
0
IREFSTEN
Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock
remains enabled when the ICS enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before
entering stop
0 Internal reference clock is disabled in stop