Datasheet
Table Of Contents
- MC9S08SH8DS_Readme
- MC9S08SH8_DSAD_Rev.1
- MC9S08SH8
- Chapter 1 Device Overview
- Chapter 2 Pins and Connections
- Chapter 3 Modes of Operation
- Chapter 4 Memory
- Chapter 5 Resets, Interrupts, and General System Control
- 5.1 Introduction
- 5.2 Features
- 5.3 MCU Reset
- 5.4 Computer Operating Properly (COP) Watchdog
- 5.5 Interrupts
- 5.6 Low-Voltage Detect (LVD) System
- 5.7 Reset, Interrupt, and System Control Registers and Control Bits
- 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)
- 5.7.2 System Reset Status Register (SRS)
- 5.7.3 System Background Debug Force Reset Register (SBDFR)
- 5.7.4 System Options Register 1 (SOPT1)
- 5.7.5 System Options Register 2 (SOPT2)
- 5.7.6 System Device Identification Register (SDIDH, SDIDL)
- 5.7.7 System Power Management Status and Control 1 Register (SPMSC1)
- 5.7.8 System Power Management Status and Control 2 Register (SPMSC2)
- Chapter 6 Parallel Input/Output Control
- 6.1 Port Data and Data Direction
- 6.2 Pull-up, Slew Rate, and Drive Strength
- 6.3 Ganged Output
- 6.4 Pin Interrupts
- 6.5 Pin Behavior in Stop Modes
- 6.6 Parallel I/O and Pin Control Registers
- 6.6.1 Port A Registers
- 6.6.1.1 Port A Data Register (PTAD)
- 6.6.1.2 Port A Data Direction Register (PTADD)
- 6.6.1.3 Port A Pull Enable Register (PTAPE)
- 6.6.1.4 Port A Slew Rate Enable Register (PTASE)
- 6.6.1.5 Port A Drive Strength Selection Register (PTADS)
- 6.6.1.6 Port A Interrupt Status and Control Register (PTASC)
- 6.6.1.7 Port A Interrupt Pin Select Register (PTAPS)
- 6.6.1.8 Port A Interrupt Edge Select Register (PTAES)
- 6.6.2 Port B Registers
- 6.6.2.1 Port B Data Register (PTBD)
- 6.6.2.2 Port B Data Direction Register (PTBDD)
- 6.6.2.3 Port B Pull Enable Register (PTBPE)
- 6.6.2.4 Port B Slew Rate Enable Register (PTBSE)
- 6.6.2.5 Port B Drive Strength Selection Register (PTBDS)
- 6.6.2.6 Port B Interrupt Status and Control Register (PTBSC)
- 6.6.2.7 Port B Interrupt Pin Select Register (PTBPS)
- 6.6.2.8 Port B Interrupt Edge Select Register (PTBES)
- 6.6.3 Port C Registers
- 6.6.1 Port A Registers
- Chapter 7 Central Processor Unit (S08CPUV2)
- 7.1 Introduction
- 7.2 Programmer’s Model and CPU Registers
- 7.3 Addressing Modes
- 7.4 Special Operations
- 7.5 HCS08 Instruction Set Summary
- Chapter 8 Analog Comparator 5-V (S08ACMPV2)
- Chapter 9 Analog-to-Digital Converter (S08ADCV1)
- 9.1 Introduction
- 9.2 External Signal Description
- 9.3 Register Definition
- 9.3.1 Status and Control Register 1 (ADCSC1)
- 9.3.2 Status and Control Register 2 (ADCSC2)
- 9.3.3 Data Result High Register (ADCRH)
- 9.3.4 Data Result Low Register (ADCRL)
- 9.3.5 Compare Value High Register (ADCCVH)
- 9.3.6 Compare Value Low Register (ADCCVL)
- 9.3.7 Configuration Register (ADCCFG)
- 9.3.8 Pin Control 1 Register (APCTL1)
- 9.3.9 Pin Control 2 Register (APCTL2)
- 9.3.10 Pin Control 3 Register (APCTL3)
- 9.4 Functional Description
- 9.5 Initialization Information
- 9.6 Application Information
- Chapter 10 Internal Clock Source (S08ICSV2)
- 10.1 Introduction
- 10.2 External Signal Description
- 10.3 Register Definition
- 10.4 Functional Description
- Chapter 11 Inter-Integrated Circuit (S08IICV2)
- Chapter 12 Modulo Timer (S08MTIMV1)
- Chapter 13 Real-Time Counter (S08RTCV1)
- Chapter 14 Serial Communications Interface (S08SCIV4)
- Chapter 15 Serial Peripheral Interface (S08SPIV3)
- Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
- Chapter 17 Development Support
- 17.1 Introduction
- 17.2 Background Debug Controller (BDC)
- 17.3 On-Chip Debug System (DBG)
- 17.4 Register Definition
- 17.4.1 BDC Registers and Control Bits
- 17.4.2 System Background Debug Force Reset Register (SBDFR)
- 17.4.3 DBG Registers and Control Bits
- 17.4.3.1 Debug Comparator A High Register (DBGCAH)
- 17.4.3.2 Debug Comparator A Low Register (DBGCAL)
- 17.4.3.3 Debug Comparator B High Register (DBGCBH)
- 17.4.3.4 Debug Comparator B Low Register (DBGCBL)
- 17.4.3.5 Debug FIFO High Register (DBGFH)
- 17.4.3.6 Debug FIFO Low Register (DBGFL)
- 17.4.3.7 Debug Control Register (DBGC)
- 17.4.3.8 Debug Trigger Register (DBGT)
- 17.4.3.9 Debug Status Register (DBGS)
- Appendix A Electrical Characteristics
- A.1 Introduction
- A.2 Parameter Classification
- A.3 Absolute Maximum Ratings
- A.4 Thermal Characteristics
- A.5 ESD Protection and Latch-Up Immunity
- A.6 DC Characteristics
- A.7 Supply Current Characteristics
- A.8 External Oscillator (XOSC) Characteristics
- A.9 Internal Clock Source (ICS) Characteristics
- A.10 Analog Comparator (ACMP) Electricals
- A.11 ADC Characteristics
- A.12 AC Characteristics
- A.13 FLASH Specifications
- A.14 EMC Performance
- Appendix B Ordering Information and Mechanical Drawings
Chapter 15 Serial Peripheral Interface (S08SPIV3)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
224 Freescale Semiconductor
Figure 15-1. MC9S08SH8 Block Diagram Highlighting the SPI Module
PTB7/SCL/EXTAL
PORT B
PTB6/SDA/XTAL
PTB5/TPM1CH1/
SS
PTB4/TPM2CH1/MISO
PTB3/PIB3/MOSI/ADP7
PTB2/PIB2/SPSCK/ADP6
PORT A
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTB1/PIB1/TxD/ADP5
PTB0/PIB0/RxD/ADP4
PORT C
PTC3/ADP11
PTC2/ADP10
PTC1/TPM1CH1/ADP9
PTC0/TPM1CH0/ADP8
PTA3/PAI3/SCL/ADP3
PTA2/PAI2/SDA/ADP2
PTA0/PIA0/TPM1CH0/ADP0/ACMP+
Pin can be enabled as part of the ganged output drive feature
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET
NOTE 1: Port B not available on 8-pin packages
SEE NOTE 1
SEE NOTE 1, 2
NOTE 2: Port C not available on 8-pin or 16-pin packages
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
HCS08 CORE
CPU
BDC
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
VOLTAGE REGULATOR
DEBUG MODULE (DBG)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
40-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
SS
TCLK
BKGD/MS
16-BIT TIMER/PWM
MODULE (TPM2)
TCLK
REAL-TIME COUNTER (RTC)
(MC9S08SH8 = 8,192 BYTES)
(MC9S08SH4 = 4096 BYTES)
(MC9S08SH8 = 512 BYTES)
ANALOG COMPARATOR
(ACMP)
ACMPO
ACMP–
ACMP+
TPM2CH0
TPM2CH1
ADP11-ADP0
16-BIT TIMER/PWM
MODULE (TPM1)
TCLK
TPM1CH0
TPM1CH1
IRQ
IRQ
(MC9S08SH4 = 256 BYTES)
NOTE 3: V
DDA
/V
REFH
and V
SSA
/V
REFL
, are double bonded to V
DD
and V
SS
respectively.
NOTES
=
SEE NOTE 3