Datasheet
Table Of Contents
- MC9S08SH8DS_Readme
- MC9S08SH8_DSAD_Rev.1
- MC9S08SH8
- Chapter 1 Device Overview
- Chapter 2 Pins and Connections
- Chapter 3 Modes of Operation
- Chapter 4 Memory
- Chapter 5 Resets, Interrupts, and General System Control
- 5.1 Introduction
- 5.2 Features
- 5.3 MCU Reset
- 5.4 Computer Operating Properly (COP) Watchdog
- 5.5 Interrupts
- 5.6 Low-Voltage Detect (LVD) System
- 5.7 Reset, Interrupt, and System Control Registers and Control Bits
- 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)
- 5.7.2 System Reset Status Register (SRS)
- 5.7.3 System Background Debug Force Reset Register (SBDFR)
- 5.7.4 System Options Register 1 (SOPT1)
- 5.7.5 System Options Register 2 (SOPT2)
- 5.7.6 System Device Identification Register (SDIDH, SDIDL)
- 5.7.7 System Power Management Status and Control 1 Register (SPMSC1)
- 5.7.8 System Power Management Status and Control 2 Register (SPMSC2)
- Chapter 6 Parallel Input/Output Control
- 6.1 Port Data and Data Direction
- 6.2 Pull-up, Slew Rate, and Drive Strength
- 6.3 Ganged Output
- 6.4 Pin Interrupts
- 6.5 Pin Behavior in Stop Modes
- 6.6 Parallel I/O and Pin Control Registers
- 6.6.1 Port A Registers
- 6.6.1.1 Port A Data Register (PTAD)
- 6.6.1.2 Port A Data Direction Register (PTADD)
- 6.6.1.3 Port A Pull Enable Register (PTAPE)
- 6.6.1.4 Port A Slew Rate Enable Register (PTASE)
- 6.6.1.5 Port A Drive Strength Selection Register (PTADS)
- 6.6.1.6 Port A Interrupt Status and Control Register (PTASC)
- 6.6.1.7 Port A Interrupt Pin Select Register (PTAPS)
- 6.6.1.8 Port A Interrupt Edge Select Register (PTAES)
- 6.6.2 Port B Registers
- 6.6.2.1 Port B Data Register (PTBD)
- 6.6.2.2 Port B Data Direction Register (PTBDD)
- 6.6.2.3 Port B Pull Enable Register (PTBPE)
- 6.6.2.4 Port B Slew Rate Enable Register (PTBSE)
- 6.6.2.5 Port B Drive Strength Selection Register (PTBDS)
- 6.6.2.6 Port B Interrupt Status and Control Register (PTBSC)
- 6.6.2.7 Port B Interrupt Pin Select Register (PTBPS)
- 6.6.2.8 Port B Interrupt Edge Select Register (PTBES)
- 6.6.3 Port C Registers
- 6.6.1 Port A Registers
- Chapter 7 Central Processor Unit (S08CPUV2)
- 7.1 Introduction
- 7.2 Programmer’s Model and CPU Registers
- 7.3 Addressing Modes
- 7.4 Special Operations
- 7.5 HCS08 Instruction Set Summary
- Chapter 8 Analog Comparator 5-V (S08ACMPV2)
- Chapter 9 Analog-to-Digital Converter (S08ADCV1)
- 9.1 Introduction
- 9.2 External Signal Description
- 9.3 Register Definition
- 9.3.1 Status and Control Register 1 (ADCSC1)
- 9.3.2 Status and Control Register 2 (ADCSC2)
- 9.3.3 Data Result High Register (ADCRH)
- 9.3.4 Data Result Low Register (ADCRL)
- 9.3.5 Compare Value High Register (ADCCVH)
- 9.3.6 Compare Value Low Register (ADCCVL)
- 9.3.7 Configuration Register (ADCCFG)
- 9.3.8 Pin Control 1 Register (APCTL1)
- 9.3.9 Pin Control 2 Register (APCTL2)
- 9.3.10 Pin Control 3 Register (APCTL3)
- 9.4 Functional Description
- 9.5 Initialization Information
- 9.6 Application Information
- Chapter 10 Internal Clock Source (S08ICSV2)
- 10.1 Introduction
- 10.2 External Signal Description
- 10.3 Register Definition
- 10.4 Functional Description
- Chapter 11 Inter-Integrated Circuit (S08IICV2)
- Chapter 12 Modulo Timer (S08MTIMV1)
- Chapter 13 Real-Time Counter (S08RTCV1)
- Chapter 14 Serial Communications Interface (S08SCIV4)
- Chapter 15 Serial Peripheral Interface (S08SPIV3)
- Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
- Chapter 17 Development Support
- 17.1 Introduction
- 17.2 Background Debug Controller (BDC)
- 17.3 On-Chip Debug System (DBG)
- 17.4 Register Definition
- 17.4.1 BDC Registers and Control Bits
- 17.4.2 System Background Debug Force Reset Register (SBDFR)
- 17.4.3 DBG Registers and Control Bits
- 17.4.3.1 Debug Comparator A High Register (DBGCAH)
- 17.4.3.2 Debug Comparator A Low Register (DBGCAL)
- 17.4.3.3 Debug Comparator B High Register (DBGCBH)
- 17.4.3.4 Debug Comparator B Low Register (DBGCBL)
- 17.4.3.5 Debug FIFO High Register (DBGFH)
- 17.4.3.6 Debug FIFO Low Register (DBGFL)
- 17.4.3.7 Debug Control Register (DBGC)
- 17.4.3.8 Debug Trigger Register (DBGT)
- 17.4.3.9 Debug Status Register (DBGS)
- Appendix A Electrical Characteristics
- A.1 Introduction
- A.2 Parameter Classification
- A.3 Absolute Maximum Ratings
- A.4 Thermal Characteristics
- A.5 ESD Protection and Latch-Up Immunity
- A.6 DC Characteristics
- A.7 Supply Current Characteristics
- A.8 External Oscillator (XOSC) Characteristics
- A.9 Internal Clock Source (ICS) Characteristics
- A.10 Analog Comparator (ACMP) Electricals
- A.11 ADC Characteristics
- A.12 AC Characteristics
- A.13 FLASH Specifications
- A.14 EMC Performance
- Appendix B Ordering Information and Mechanical Drawings
Chapter 4 Memory
MC9S08SH8 MCU Series Data Sheet, Rev. 3
40 Freescale Semiconductor
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address
Register
Name
Bit 7 654321Bit 0
0x0000 PTAD
0 0 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0x0001 PTADD
0 0 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0x0002 PTBD
PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0x0003 PTBDD
PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
0x0004 PTCD
0 0 0 0 PTCD3 PTCD2 PTCD1 PTCD0
0x0005 PTCDD
0 0 0 0 PTCDD3 PTCDD2 PTCDD1 PTCDD0
0x0006–
0x000D
Reserved
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x000E ACMPSC
ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0
0x000F Reserved
— — — — — — — —
0x0010 ADSC1
COCO AIEN ADCO ADCH
0x0011 ADSC2
ADACT ADTRG ACFE ACFGT — — — —
0x0012 ADRH
0 0 0 0 0 0 ADR9 ADR8
0x0013 ADRL
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0x0014 ADCVH
0 0 0 0 0 0 ADCV9 ADCV8
0x0015 ADCVL
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
0x0016 ADCFG
ADLPC ADIV ADLSMP MODE ADICLK
0x0017 APCTL1
ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
0x0018 APCTL2
0 0 0 0 ADPC11 ADPC10 ADPC9 ADPC8
0x0019 Reserved
— — — — — — — —
0x001A IRQSC
0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
0x001B Reserved
— — — — — — — —
0x001C MTIMSC
TOF TOIE TRST TSTP 0 0 0 0
0x001D MTIMCLK
0 0 CLKS PS
0x001E MTIMCNT
CNT
0x001F MTIMMOD
MOD
0x0020 TPM1SC
TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0021 TPM1CNTH
Bit 15 14 13 12 11 10 9 Bit 8
0x0022 TPM1CNTL
Bit 7 654321Bit 0
0x0023 TPM1MODH
Bit 15 14 13 12 11 10 9 Bit 8
0x0024 TPM1MODL
Bit 7 654321Bit 0
0x0025 TPM1C0SC
CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0026 TPM1C0VH
Bit 15 14 13 12 11 10 9 Bit 8
0x0027 TPM1C0VL
Bit 7 654321Bit 0
0x0028 TPM1C1SC
CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x0029 TPM1C1VH
Bit 15 14 13 12 11 10 9 Bit 8
0x002A TPM1C1VL
Bit 7 654321Bit 0
0x002B–
0x0037
Reserved
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