Datasheet

Chapter 7 Central Processor Unit (S08CPUV3)
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor 105
BLE rel
Branch if Less Than or Equal To
(if Z | (N ⊕ V) = 1) (Signed)
REL 93 rr 3 ppp –11– ––––
BLO rel Branch if Lower (if C = 1) (Same as BCS) REL 25 rr 3 ppp –11– ––––
BLS rel Branch if Lower or Same (if C | Z = 1) REL 23 rr 3 ppp –11– ––––
BLT rel Branch if Less Than (if N ⊕ V = 1) (Signed) REL 91 rr 3 ppp –11– ––––
BMC rel Branch if Interrupt Mask Clear (if I = 0) REL 2C rr 3 ppp –11– ––––
BMI rel Branch if Minus (if N = 1) REL 2B rr 3 ppp –11– ––––
BMS rel Branch if Interrupt Mask Set (if I = 1) REL 2D rr 3 ppp –11– ––––
BNE rel Branch if Not Equal (if Z = 0) REL 26 rr 3 ppp –11– ––––
BPL rel Branch if Plus (if N = 0) REL 2A rr 3 ppp –11– ––––
BRA rel Branch Always (if I = 1) REL 20 rr 3 ppp –11– ––––
BRCLR n,opr8a,rel Branch if Bit n in Memory Clear (if (Mn) = 0)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd
rr
dd
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
–11– –––
BRN rel Branch Never (if I = 0) REL 21 rr 3 ppp –11– ––––
BRSET n,opr8a,rel Branch if Bit n in Memory Set (if (Mn) = 1)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
–11– –––
BSET n,opr8a Set Bit n in Memory (Mn ← 1)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
–11–
–
–––
BSR rel
Branch to Subroutine
PC ← (PC) + $0002
push (PCL); SP ← (SP) – $0001
push (PCH); SP ← (SP) – $0001
PC ← (PC) + rel
REL AD rr 5 ssppp –11– ––––
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and... Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E 61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
5
6
rpppp
pppp
pppp
rpppp
rfppp
prpppp
–11– ––––
Table 7-2. Instruction Set Summary (Sheet 3 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
V 1 1 HI N Z C