Datasheet

Chapter 7 Central Processor Unit (S08CPUV3)
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
108 Freescale Semiconductor
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E 68
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
 11 ––  
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E 64
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
 11 ––0 
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,
opr8a
Move
(M)
destination
← (M)
source
In IX+/DIR and DIR/IX+ Modes,
H:X ← (H:X) + $0001
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
5
4
5
rpwpp
rfwpp
pwpp
rfwpp
011– –  –
MUL
Unsigned multiply
X:A ← (X) × (A)
INH 42 5 ffffp –110 –––0
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate M ← – (M) = $00 – (M)
(Two’s Complement) A ← – (A) = $00 – (A)
X ← – (X) = $00 – (X)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E 60
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
 11 ––  
NOP No Operation — Uses 1 Bus Cycle INH 9D
1 p –11–
–
–––
NSA
Nibble Swap Accumulator
A ← (A[3:0]:A[7:4])
INH 62 1 p –11– ––––
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
Inclusive OR Accumulator and Memory
A ← (A) | (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9E DA
9E EA
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
011– –  –
PSHA
Push Accumulator onto Stack
Push (A); SP ← (SP) – $0001
INH 87 2 sp –11– ––––
PSHH
Push H (Index Register High) onto Stack
Push (H); SP ← (SP) – $0001
INH 8B 2 sp –11– ––––
PSHX
Push X (Index Register Low) onto Stack
Push (X); SP ← (SP) – $0001
INH 89 2 sp
–11– ––––
PULA
Pull Accumulator
from Stack
SP ← (SP +
$0001); Pull (A)
INH 86 3 ufp –11– ––––
PULH
Pull H (Index Register High) from Stack
SP ← (SP + $0001); Pull (H)
INH 8A 3 ufp –11– ––––
PULX
Pull X (Index Register Low) from Stack
SP ← (SP + $0001); Pull (X)
INH 88 3 ufp –11– ––––
Table 7-2. Instruction Set Summary (Sheet 6 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
V 1 1 HI N Z C
C
b0
b7
0
b0
b7
C0