Datasheet

MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor 187
12.1.1 Features
The SLIC includes these distinctive features:
• Full LIN message buffering of identifier and 8 data bytes
• Automatic bit rate and LIN message frame synchronization:
— No prior programming of bit rate required, 1–20 kbps LIN bus speed operation
— All LIN messages will be received (no message loss due to synchronization process)
— Input clock tolerance as high as ±50%, allowing internal oscillator to remain untrimmed
— Incoming break symbols always allowed to be 10 or more bit times without message loss
— Supports automatic software trimming of internal oscillator using LIN synchronization data
• Automatic processing and verification of LIN SYNCH BREAK and SYNCH BYTE
• Automatic checksum calculation and verification with error reporting
• Maximum of two interrupts per standard LIN message frame with no errors
• Full LIN error checking and reporting
• High-speed LIN capability up to 83.33 kbps to 120.00 kbps
1
• Configurable digital receive filter
• Streamlined interrupt servicing through use of a state vector register
• Switchable UART-like byte transfer mode for processing bytes one at a time without LIN message
framing constraints
• Enhanced checksum (includes ID) generation and verification
1. Maximum bit rate of SLIC module dependent upon frequency of SLIC input clock.