Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Flash EEPROM 256K
MC9S12DP256 — Revision 1.1  
Flash EEPROM 256K
Banked Register A register operating on one flash block which shares the same register 
address as the equivalent registers for the other flash blocks. The active 
register bank is selected by two bank-select bits in the unbanked register 
space.
Unbanked 
Register
A register which operates on all flash blocks.
Command 
Sequence
Three-step MCU instructions sequence to program or erase the Flash.
Overview
The 256K flash module is comprised of four 64K bytes blocks. They 
serve as electrically erasable and programmable, non-volatile program 
and data memory. The flash EEPROM is ideal for program and data 
storage for single-chip applications allowing for field reprogramming 
without requiring external programming voltage sources.
Each 64K byte flash block is arranged in a 32K by 16-bit configuration 
and may be read as either bytes, aligned words or misaligned words. 
Access time is one bus cycle for byte, and aligned word and two bus 
cycles for misaligned word read. Write operations for program or erase 
are only allowed as aligned word accesses. Each 64K block is organized 
in 1024 rows of 32 words. An erase sector contains 8 rows or 512 bytes. 
The erase mode supports erase sector as small as 512 bytes as well as 
mass erase of each 64K byte block. An erased word reads $FFFF and 
a programmed word reads $0000.
The programming voltage required to program and erase the flash is 
generated internally by on-chip charge pumps. Program and erase 
operations are performed by a command driven interface from the 
microcontroller using an internal state machine. All flash blocks can be 
programmed or erased at the same time, however it is not possible to 
read from a flash block while it is being erased or programmed.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
 Go to: www.freescale.com
nc...










