Datasheet

MC9S12DT128B Device User Guide — V01.09
Figure A-6 SPI Master Timing (CPHA =1)
Table A-18 SPI Master Mode Timing Characteristics
1
NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-19.
Conditions are shown in Table A-4 unless otherwise noted, C
LOAD
= 200pF on all outputs
Num C Rating Symbol Min Typ Max Unit
1 P Operating Frequency
f
op
DC 1/4
f
bus
1P
SCK Period t
sck
= 1./f
op
t
sck
4 2048
t
bus
2 D Enable Lead Time
t
lead
1/2—
t
sck
3 D Enable Lag Time
t
lag
1/2
t
sck
4 D Clock (SCK) High or Low Time
t
wsck
t
bus
− 30 1024 t
bus
ns
5 D Data Setup Time (Inputs)
t
su
25 ns
6 D Data Hold Time (Inputs)
t
hi
0ns
9 D Data Valid (after SCK Edge)
t
v
25 ns
10 D Data Hold Time (Outputs)
t
ho
0ns
11 D Rise Time Inputs and Outputs
t
r
25 ns
12 D Fall Time Inputs and Outputs
t
f
25 ns
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
5 6
MSB IN
2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT
2
MASTER LSB OUT
BIT 6 . . . 1
4
4
9
11 12
10
PORT DATA
(CPOL
= 0)
(CPOL
= 1)
PORT DATA
SS
1
(OUTPUT)
2
12 11 3
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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