Datasheet

MC9S12DT128B Device User Guide — V01.09

Section 3 System Clock Description

3.1 Overview

The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.

Figure 3-1 shows the clock connections from the CRG to all modules.

Consult the CRG Block User Guide for details on clock generation.

Figure 3-1 Clock Connections

CRG

bus clock

core clock

EXTAL

XTAL

oscillator clock

S12_CORE

IIC

RAM

SCI0, SCI1

PWM

ATD0, 1

Flash

ECT

BDLC

SPI0, 1

CAN0, 1, 4

PIM

EEPROM

BDM

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