Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pulse Width Modulator (PWM)
Functional Description
  MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
When PWMSCLB = $00, PWMSCLB value is considered a full scale 
value of 256. Clock B is thus divided by 512.
As an example, consider the case in which the user writes $FF into the 
PWMSCLA register. Clock A for this case will be E divided by 4. A pulse 
will occur at a rate of once every 255x4 E cycles. Passing this through 
the divide by two circuit produces a clock signal at an E divided by 2040 
rate. Similarly, a value of $01 in the PWMSCLA register when clock A is 
E divided by 4 will produce a clock at an E divided by 8 rate.
 Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down 
counter to be re-loaded. Otherwise, when changing rates the counter 
would have to count down to $01 before counting at the proper rate. 
Forcing the associated counter to re-load the scale register value every 
time PWMSCLA or PWMSCLB is written prevents this.
CAUTION:
Writing to the scale registers while channels are operating can cause 
irregularities in the PWM outputs.
Clock Select Each PWM channel has the capability of selecting one of two clocks. For 
channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For 
channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock 
selection is done with the PCLKx control bits in the PWMCLK register.
CAUTION:
Changing clock control bits while channels are operating can cause 
irregularities in the PWM outputs.
PWM Channel 
Timers
The main part of the PWM module are the actual timers. Each of the 
timer channels has a counter, a period register and a duty register (each 
are 8-bit). The waveform output period is controlled by a match between 
the period register and the value in the counter. The duty is controlled by 
a match between the duty register and the counter value and causes the 
state of the output to change during the period. The starting polarity of 
the output is also selectable on a per channel basis. Shown below in 
Figure 47 is the block diagram for the PWM timer 
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
 Go to: www.freescale.com
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