Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pinout and Signal Description
Signal Descriptions
  MC9S12DP256 — Revision 1.1
Pinout and Signal Description
MCU will recognize another interrupt as soon as the interrupt mask bit in 
the MCU is cleared (normally upon return from an interrupt). 
Mode Select 
(MODA, MODB, 
and MODC)
The state of these pins during reset determine the MCU operating mode. 
After reset, MODA and MODB can be configured as instruction queue 
tracking signals IPIPE0 and IPIPE1 in expanded modes. MODA, and 
MODB have active pulldowns during reset. MODC has the pull-up on the 
pin enabled after reset. 
Single-Wire 
Background Mode 
Pin (BKGD) shared 
with MODC
The BKGD pin receives and transmits serial background debugging 
commands. A special self-timing protocol is used.Out of reset the pin is 
configured as input with internal pull-up enabled.
NOTE:
The resistance of the internal pull-up may be too high depending on the 
speed and the load to ensure proper BDM communication. In this case 
an additional external pull-up resistor must be provided.
External Address 
and Data Buses 
(ADDR[15:0] and 
DATA[15:0])
External bus pins share functions with general-purpose I/O ports A and 
B. In single-chip operating modes, the pins can be used for 
general-purpose I/O; in expanded modes, the pins are used for the 
external buses.
In expanded wide mode, ports A and B are used for multiplexed 16-bit 
data and address buses. PA[7:0] correspond to 
ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0]. 
In expanded narrow mode, ports A and B are used for the16-bit address 
bus, and an 8-bit data bus is multiplexed with the most significant half of 
the address bus on port A. In this mode, 16-bit data is handled as two 
back-to-back bus cycles, one for the high byte followed by one for the 
low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or 
DATA[7:0], depending on the bus cycle. The state of the address pins 
should be latched at the rising edge of E. To allow for maximum address 
setup time at external devices, a transparent latch should be used.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
 Go to: www.freescale.com
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