Datasheet

MSCAN
Register Descriptions
MC9S12DP256 — Revision 1.1
MSCAN
until SLPRQ is cleared by the CPU or, depending on the setting of
WUPE bit, the MSCAN detects bus activity on CAN and clears the
SLPRQ itself.
1 = Sleep Mode Request – The MSCAN locks in idle state.
0 = Running – The MSCAN functions normally.
NOTE: The MCU cannot clear the SLPRQ bit before the MSCAN has entered
Sleep Mode (SLPRQ=1 and SLPAK=1)
INITRQ — Initialization Mode Request
When this bit is set by the CPU, the MSCAN skips to Initialization
Mode (see MSCAN Initialization Mode). Any ongoing transmission or
reception is aborted and synchronization to the bus is lost. The
module indicates entry to Initialization Mode by setting INITAK=1 (see
MSCAN Control 1 Register (CANCTL1)).
The following registers enter their hard reset state and restore their
default values: CANCTL0
1
, CANRFLG
2
, CANRIER
3
, CANTFLG,
CANTIER, CANTARQ, CANTAAK, CANTBSEL.
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC,
CANIDAR0–7, CANIDMR0–7 can only be written by the CPU when
the MSCAN is in Initialization Mode (INITRQ=1 and INITAK=1). The
values of the error counters are not affected by initialization.
When this bit is cleared by the CPU, the MSCAN restarts and then
tries to synchronize to the CAN bus. If the MSCAN is not in bus-off
state, it synchronizes after 11 consecutive recessive bits on the bus;
if the MSCAN is in bus-off state it continues to wait for 128
occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG
or CANTIER must only be done after Initialization Mode is left, which
is INITRQ=0 and INITAK=0.
1 = MSCAN in initialization state.
0 = Normal operation.
1. except the INITRQ and SLPRQ bits
2. The TSTAT1, TSTAT0 bits are not affected by Initialization Mode
3. The RSTAT1, RSTAT0 bits are not affected by Initialization Mode
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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