Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Analog to Digital Converter
MC9S12DP256 — Revision 1.1  
Analog to Digital Converter
the input pins at the digital sampling time that don’t meet the V
IL
 or V
IH
specification will return unknown digital values. A read of the PORTAD1 
may affect the accuracy of an in progress sample period but will not 
affect an in progress A/D conversion.
There is a digital, 8-bit, input-only port associated with the ATD. It is 
accessed through the 8-bit Port Data Register (PORTAD1). The number 
of bits utilized in the port register depends on the number of analog 
channels implemented with the 8 channel ATD module.
Clock Prescale 
Function
To keep the ATD module’s conversion clock within the specified 
frequency range, a clock prescale function is available. This function 
divides the ATD module clock by a program selectable binary constant 
in order to generate the ATD module’s conversion clock. The ATD 
conversion clock is used to clock both the sample machine and the A/D 
machine.
Another important benefit of the prescaled clock feature is that it allows 
the user control over the sample period. Note that if the prescale function 
is used this way, the conversion time is also affected.
The prescale feature is based on a 5 bit modulus counter and will divide 
the clock by an integer value between 1 and 32. The final clock 
frequency is obtained with a further division by 2. Therefore, the highest 
possible ATD conversion clock frequency is one half of the ATD module 
clock frequency, but cannot be faster than the maximum ATD operating 
frequency as defined in the electrical specification. The maximum speed 
of ATD conversion frequency is 2 MHz. Table 102 lists the prescale 
value for various setting of the control register bits. Figure 109 is a block 
diagram of the clock prescale logic. 
The ATD conversion clock and the ATD module clock have a direct 
phase relationship. However, the ATD module operates as if it is 
effectively asynchronous to IP bus cycles.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
 Go to: www.freescale.com
nc...










