Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Resetting to idle mode defines the only exception of the reset control
bit condition to the general (bus) reset condition. The reset control bit
does not initialize the ADPU bit to its reset condition and therefore
does not power down the module. This exception allows the module
to remain active for other test operations.
ATDCLK — Display the state of the ATD conversion clock
This bit can be used to display the state of the ATD conversion clock
ATDCLK when in special mode. Note that this bit cannot be written to.
Note further that ATDCLK will reset upon the start of a new
conversion sequence.
SC — Special Channel Conversion Mode
1 = Perform special channel ATD conversion.
0 = Perform ATD conversion on an analog input channel.
SC determines if the ATD module performs ATD conversions on any
of the analog input channels (normal operation) or whether it performs
a conversion on one of the defined, special channels. The special
channels are normally used to test the ATD machine and include
converting the high and low reference potentials for the module. The
control bits CC/CB/CA are used to indicate which special channels is
to be converted. Table 106 lists the currently available special
channels. The last column in the table denote the expected digital
code that should be generated by the special conversion for 8-bit
resolution.
Table 106 Special Channel Conversion Select Coding
CC CB CA
Special
Channel
Expected
Digital Result Code
0 X X reserved –
1 0 0 VRH $FF
1 0 1 VRL $00
1 1 0 (VRH + VRL)/2 $80
1 1 1 reserved –
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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