Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pinout and Signal Description
MC9S12DP256 — Revision 1.1  
Pinout and Signal Description
clearing a bit in DDRK makes the corresponding bit in port K an input. 
The default reset state of DDRK is all zeroes.
NOTE:
The ports H, J, M, P, S, T can be configured in a very flexible way. For a 
full and detailed overview refer to Section Port Integration Module.
Port M for MSCAN 
and BDLC
There are four identical MSCAN ports and a BDLC module sharing the 
multiplex port M. The port pins act as general purpose I/O if MSCAN and 
BDLC are disabled.
ATD PORT This port is an analog input interface to the analog-to-digital subsystem. 
The digital function of the ports must explicitly be enabled on per pin 
basis using a control register in the ADC module. When the port data 
registers are read, they contain the digital levels appearing on the input 
pins at the time of the read. Input pins with signal potentials not meeting 
V
IL
 or V
IH
 specifications will have an indeterminate value.
Use of any ATD port pin except ETRIG for digital input does not preclude 
the use of any other port pin for analog input. Note that the digital/analog 
multiplexing function is performed in the input pad. The port registers are 
connected to the input pads through tristate buffers. These buffers are 
only activated when the port is configured as digital pin so that analog 
signal potentials on the input pins will not cause the buffers to draw 
excess supply current.
Port S for SCI0, SCI1 
and SPI0
There are two identical SCI ports. Each SCI module uses two external 
pins. The RxD0, RxD1 and TxD0, TxD1pins share general purpose port 
SCI P[3:0]. TxD0, TxD1 are available for general-purpose I/O when it is 
not configured for transmitter operation. RxD0, RxD1 are available for 
general-purpose I/O when it is not configured for receiver operation.
The SPI0 module uses four external pins. SS0
, SCK0, MOSI0, and 
MISO0 pins share general purpose port PS[7:4].
Timer Port The timer module has eight external pins: PT[7:0]_IOC[7:0], for input 
capture and output compare functions. Two of the pins are also the pulse 
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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