Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link 
MC9S12DP256 — Revision 1.1  
Byte Data Link Controller Module
Figure 117 J1850 Bus Message Format (VPW)
SAE J1850 states that each message has a maximum length of 101 bit 
times or 12 bytes (excluding SOF, EOD, NB and EOF).
SOF – Start of 
Frame Symbol
All messages transmitted onto the J1850 bus must begin with an long 
active SOF symbol. This indicates to any listeners on the J1850 bus the 
start of a new message transmission. The SOF symbol is not used in the 
CRC calculation.
Data – In Message 
Data Bytes
The data bytes contained in the message include the message 
priority/type, message I.D. byte, and any actual data being transmitted 
to the receiving node. The message format used by the BDLC is similar 
to the 3 Byte Consolidated Header message format outlined by the SAE 
J1850 document. See SAE J1850 – Class B Data Communications 
Network Interface, for more information about 1 and 3 Byte Headers.
Messages transmitted by the BDLC onto the J1850 bus must contain at 
least one data byte, and therefore can be as short as one data byte and 
one CRC byte. Each data byte in the message is 8 bits in length, 
transmitted MSB to LSB. 
CRC – Cyclical 
Redundancy 
Check Byte
This byte is used by the receiver(s) of each message to determine if any 
errors have occurred during the transmission of the message. The BDLC 
calculates the CRC byte and appends it onto any messages transmitted 
onto the J1850 bus, and also performs CRC detection on any messages 
it receives from the J1850 bus.
CRC generation uses the divisor polynomial X
8
+X
4
+X
3
+X
2
+1. The 
remainder polynomial is initially set to all ones, and then each byte in the 
message after the SOF symbol is serially processed through the CRC 
generation circuitry. The one’s complement of the remainder then 
SOF
EOD
EOF
Priority
Message
Data
n
CRC IFR
IFS
Idle
Idle
ID (Data1)
(Data0)
Optional
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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