Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link Controller Module
Functional Description
  MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Valid EOD Symbol If the passive to active transition beginning the next data bit or symbol 
occurs between T
rvp3(Min)
 and T
rvp3(Max)
, the current symbol would be 
considered a valid EOD symbol.See Figure 119(4).
Figure 120 J1850 VPW EOF and IFS Symbols
Valid EOF & IFS 
Symbol
In Figure 120(1), if the passive to active transition beginning the SOF 
symbol of the next message occurs between T
rv4(Min)
 and T
rv4(Max)
, the 
current symbol will be considered a valid EOF symbol. 
If the passive to active transition beginning the SOF symbol of the next 
message occurs after T
rv5(Min)
, the current symbol will be considered a 
valid EOF symbol followed by a valid IFS symbol. See Figure 120(2). All 
nodes must wait until a valid IFS symbol time has expired before 
beginning transmission. However, due to variations in clock frequencies 
and bus loading, some nodes may recognize a valid IFS symbol before 
others, and immediately begin transmitting. Therefore, anytime a node 
waiting to transmit detects a passive to active transition once a valid 
EOF has been detected, it should immediately begin transmission, 
initiating the arbitration process.
Idle Bus If the passive to active transition beginning the SOF symbol of the next 
message does not occur before T
tv5(Min)
, the bus is considered to be 
idle, and any node wishing to transmit a message may do so 
immediately.
(2) Valid EOF + IFS Symbol 
280µs
300µs
T
rv4(Min)
T
rv4(Max)
(1) Valid EOF Symbol 
Active
Passive
Active
Passive
T
rv5(Min)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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